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Altera Experts Discuss Transceiver Technology, Floating Point DSP and Signal Integrity at DesignCon 2012

(Logo: http://photos.prnewswire.com/prnh/20101012/SF78952LOGO)

    When:                                   January 30 to February 2,
                                            2012
    Where:                                 Santa Clara Convention Center
                                           Santa Clara, Calif.

Panel Discussions:

Monday, January 30

4:45 p.m. - 6:00 p.m., Ballroom E/F

    --  The Case of the Closing Eye - De-mystifying the Measurement Complexity

Modern communication systems employ complex receivers that open the "closed EYE". Closed Eyes are difficult to specify so standards bodies have incorporated reference equalizers to measure the receiver stress in terms of an open EYE. Altera's Mike Li will join this panel to explore why differences must exist between the reference EQ and efficient silicon implementation.

Tuesday, January 31

3:45 - 5:00 p.m., Ballroom G

    --  The Future of Measurements in High-Speed Serial Links

Altera's Daniel Chow will participate on this panel, which will feature engineers who characterize components that run at today's highest speeds. Panelists will share their experiences at making measurements and how they combine instruments to gain as much information as possible about a signal or system.

TechForum Tutorial Session:

Monday, January 30

9:00 a.m. - 12:00p.m., Ballroom F

    --  Design & Verification for High-Speed I/Os at Multiple to >32 Gbps With
        Jitter, Signal Integrity

This TechForum tutorial will review the latest design and verification developments, as well as architecture, circuit, and deep submicron process (40 nm, 28 nm) technology advancements for high-speed links, with an emphasis on jitter and signal integrity for up to 10- to 32-Gbps high-speed I/Os (e.g., GbE (10G, 100G), CEI/OIF (11G, 25-28G), OTN/OTU5 (32 G), Fibre Channel (16G, 32G), and PCI Express (8G, 16G)).

Paper Sessions:

Tuesday, January 31

8:30 a.m. - 9:10 a.m., Great America K

    --  A 12.5-Gbps TX FFE with Floating Taps in 28-nm CMOS

Tuesday, January 31

10:15 a.m. - 10:55 a.m., Ballroom F

    --  PDN Resonance Calculator for Chip, Package and Board

Tuesday, January 31

11:05 a.m. - 11:45 a.m., Ballroom E

    --  Worst-Case Patterns for High-Speed Simulation and Measurement

Tuesday, January 31

2:50 p.m. - 3:30 p.m., Great America 2

    --  Investigation of Performance Challenge and Opportunity to TSV Silicon
        Interposer in 3D Integration Systems

Wednesday, February 1

10:15 A.M. - 10:55 A.M., Great America 1

    --  FPGA Implementation of Floating-Point Matrix Inversion

Wednesday, February 1

10:15 a.m. - 10:55 a.m., Great America 2

    --  Reflection-Induced Jitter Separation Methodology and Its Applications

Wednesday, February 1

11:05 a.m. - 11:45 a.m., Ballroom E

    --  A New Energy-Efficient Unified High-Speed Link Architecture

Thursday, February 2

9:00 a.m. - 9:40 a.m., Ballroom G

    --  PDN Noise to Jitter Transfer in High-Speed Transceiver

Thursday, February 2

9:50 a.m. - 10:30 a.m., Ballroom H

    --  The Effects of a Linear Equalizer on Uncorrelated Jitter and Noise and
        Implications for Test

About DesignCon

DesignCon is the largest meeting of board designers, and the only event to address chip design engineers' chip/system/package challenges. DesignCon features over 100 tutorials and technical paper sessions in 14 conference tracks focused on the pervasive nature of signal integrity at all levels of electronic design: chip, package, board, and system. For more information about DesignCon visit www.designcon.com.

About Altera

Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

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Editor Contact:

Steve Gabriel

Altera Corporation

(408) 544-6846

newsroom@altera.com

SOURCE Altera Corporation